IDT72225LB25G

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Product Technical Specifications

Source Content uid

IDT72225LB25G

Rohs Code

No

Part Life Cycle Code

Obsolete

Part Package Code

PGA

Package Description

CAVITY-UP, PGA-68

Pin Count

68

Reach Compliance Code

not_compliant

ECCN Code

EAR99

HTS Code

8542.32.00.71

Access Time-Max

15 ns

Clock Frequency-Max (fCLK)

40 MHz

Cycle Time

25 ns

JESD-30 Code

S-CPGA-P68

JESD-609 Code

e0

Length

29.464 mm

Memory Density

18432 bit

Memory IC Type

OTHER FIFO

Memory Width

18

Number of Functions

1

Number of Terminals

68

Number of Words

1024 words

Number of Words Code

1000

Operating Mode

SYNCHRONOUS

Operating Temperature-Max

70 °C

Operating Temperature-Min

Organization

1KX18

Output Characteristics

3-STATE

Output Enable

YES

Package Body Material

CERAMIC, METAL-SEALED COFIRED

Package Code

PGA

Package Equivalence Code

PGA68,11X11

Package Shape

SQUARE

Package Style

GRID ARRAY

Parallel/Serial

PARALLEL

Power Supplies

5 V

Qualification Status

Not Qualified

Seated Height-Max

5.207 mm

Standby Current-Max

0.07 A

Supply Current-Max

0.2 mA

Supply Voltage-Max (Vsup)

5.5 V

Supply Voltage-Min (Vsup)

4.5 V

Supply Voltage-Nom (Vsup)

5 V

Surface Mount

NO

Technology

CMOS

Temperature Grade

COMMERCIAL

Terminal Finish

Tin/Lead (Sn/Pb)

Terminal Form

PIN/PEG

Terminal Pitch

2.54 mm

Terminal Position

PERPENDICULAR

Width

29.464 mm